Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 155

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 77. MultiProcessor Control Register (UxCTL1 with MSEL = 000b)
PS028702-1210
Bits
2
1
0
Bits
Field
RESET
R/W
ADDR
LIN-UART Control 1 Registers
Description (Continued)
SBRK – Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit. In
standard UART mode, the duration of the break is determined by how long software leaves this
bit asserted. Also the duration of any required Stop bits following the break must be timed by
software before writing a new byte to be transmitted to the transmit data register. In LIN mode,
the master sends a Break character by asserting SBRK. The duration of the break is timed by
hardware and the SBRK bit is deasserted by hardware when the Break is completed. The
duration of the Break is determined by the TxBreakLength field of the LIN control register. One
or two Stop bits are automatically provided by the hardware in LIN mode as defined by the Stop
bit.
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP – Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN – Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
MPMD[1]
R/W
7
0
Multiple registers (see Tables 77 through 79) are accessible by a single bus address. The
register selected is determined by the mode select (
additional control over the LIN-UART operation.
Multiprocessor Control Register (LIN-UART Control 1 Register with
MSEL = 000b)
When
IRDA mode, baud rate timer mode as well as other features which applies to multiple
modes.
MSEL
MPEN
R/W
6
0
=
000b
MPMD[0]
, this register provides control for UART MULTIPROCESSOR mode,
FF_E203H, FF_E213H with MSEL = 000b
R/W
5
0
P R E L I M I N A R Y
MPBT
R/W
4
0
DEPOL
R/W
Z16FMC Series Motor Control MCUs
3
0
MSEL
BRGCTL
) field. These registers provide
R/W
2
0
Product Specification
RDAIRQ
R/W
1
0
LIN-UART
IREN
R/W
0
0
133