Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 285

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
DEBUG HALT Mode
Reading and Writing Memory
A clock change invalidates the baud reload value. Communication cannot continue until a
new autobaud reload value is set. As a result, the device automatically sends a serial break
to reset the communication link whenever a clock change occurs.
During debugging, it is appropriate to stop the CPU from executing instructions by plac-
ing the device into DEBUG HALT mode. The operating characteristics of the Z16FMC
devices in DEBUG HALT mode are:
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Entering DEBUG HALT mode
The device enters DEBUG HALT mode by any of the following operations:
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Exiting DEBUG HALT mode
The device exits DEBUG HALT mode by any of the following operations:
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Most debugging functions are accomplished by reading and writing control registers. The
OCD hardware is capable of reading and writing memory when the CPU is running.
When a read or write request from the OCD hardware occurs, the OCD steals the bus for
the number of cycles needed to complete the read or write operation. This bus stealing
occurs on a per byte basis, not a per command basis. Because the debugger operates seri-
ally, it takes several clock cycles to transmit or receive a character.
If the debugger receives a command to read or write a block of memory, it will not steal
the bus for the entire read or write command. The debugger will only steal the bus for a
short period of time for each data byte. A debug write cycle will occur after a byte has
The CPU fetch unit stops, idling the CPU
All enabled on-chip peripherals operate unless in STOP mode
Constantly refreshes the WDT, if enabled
Write the DBGHALT bit in the DBGCTL register to 1 using the OCD interface
CPU execution of
Hardware breakpoint match
Clearing the
Power-on reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset
DBGHALT
BRK
P R E L I M I N A R Y
bit in the DBGCTL register to 0
instruction (when enabled)
Z16FMC Series Motor Control MCUs
Product Specification
On-Chip Debugger
263