Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 201

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Figure 34. Data Transfer Format – Master Write Transaction with a 7-Bit Address
Address
Slave
Master Write Transaction with a 7-Bit Address
Figure 34 displays the data transfer format from a Master to a 7-bit addressed Slave.
Follow the procedure below to perform a Master transmit operation to a 7-bit addressed
Slave.
1. Software initializes the MODE field in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
5. Software sets the
6. The I
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the transmit data into the I
10. The I
11. The I
12. The I
with either 7-bit or 10-bit slave address. The MODE field selects the address width for
this node when addressed as a Slave, not for the remote Slave. Software asserts the
IEN bit in the I
to the I
Register.
asserts.
High period of SCL. The I
If the slave does not acknowledge the address byte, the I
bit in the I
the I
the STOP bit and clearing the TXI bit. The I
register, sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
I
2
W=0
C Data Register.
2
2
2
2
2
2
2
C State Register. Software responds to the Not Acknowledge interrupt by setting
C Slave sends an acknowledge (by pulling the SDA signal Low) during the next
C interrupt asserts, because the I
C Controller sends the Start condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out the SDA signal.
C Controller loads the contents of the I
2
C Data Register.
A
2
C Interrupt Status Register, sets the ACKV bit and clears the ACK bit in
2
C Control Register.
START
Data
P R E L I M I N A R Y
bit of the I
2
C Controller sets the ACK bit in the I
2
A
C Shift Register with the contents of the I
2
2
C Control Register.
C Control Register to enable Transmit interrupts.
2
Data
C Data Register is empty.
Z16FMC Series Motor Control MCUs
2
2
2
C Mode Register for Master/Slave mode
C Controller flushes the transmit data
C Shift Register with the contents of the
A
2
C Slave.
2
2
C Data Register.
C Controller sets the
I2C Master/Slave Controller
Data
Product Specification
2
C State Register.
A/A
2
C Data
NCKI
P/S
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