Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 212

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Slave Address
1st Byte
Figure 41. Data Transfer Format – Slave Transmit Transaction with 10-Bit Address
9. Software responds to the Not Acknowledge interrupt by clearing the
10. When the Master completes the final acknowledge cycle, it asserts the STOP or
11. The Slave I
12. Software responds to the STOP/RESTART interrupt by reading the I2CISTAT register
Slave Transmit (Master Read) Transaction with 10-Bit Address
Figure 41 displays the data transfer format for a Master reading data from a Slave with 10-
bit addressing.
The following procedure describes the I
10-bit addressing mode, transmitting data to the bus Master:
1. Software configures the controller for operation as a Slave in 10-bit addressing mode.
2. The Master initiates a transfer, sending the first address byte. The Slave mode I
most significant data bit, the Slave I
register is written.
When the Slave receives a Not Acknowledge instruction, the I
NCKI
I2CCTL register and by asserting the
data register.
RESTART condition on the bus.
I2CISTAT register).
which clears the
a. Initialize the MODE field in the I
b. Optionally set the
c. Initialize the
d. Set
e. Program the Baud Rate High and Low Byte registers for the I
Controller recognizes the start of a 10-bit address with a match to
the R/W bit = 0 (write from Master to Slave). The I
indicating that it is available to accept the transaction.
W=0 A Slave Address
Master/Slave mode with 10-bit addressing.
I2CMODE register.
bit in the I2CISTAT register and generates the Not Acknowledge interrupt.
IEN
2
C Controller asserts the STOP/RESTART interrupt (set
= 1,
2nd Byte
SPRS
NAK
SLA
[7:0] bits in the I2CSLVAD register and
= 0 in the I
GCE
P R E L I M I N A R Y
bit.
bit.
A S Slave Address
2
C Control Register.
2
2
C Master/Slave Controller operating as a Slave in
C Controller holds SCL Low until the data
1st Byte
2
FLUSH
C Mode Register for either Slave-only mode or
Z16FMC Series Motor Control MCUs
bit of the I2CCTL register to empty the
R=1
2
C Controller acknowledges,
A
I2C Master/Slave Controller
Product Specification
Data
SLA
2
C Controller sets the
SLA
2
[9:8] in the
C baud rate.
SPRS
A
TXI
[9:8] and detects
Data
bit in the
bit in
2
A P
C
190