STA310 STMicroelectronics, STA310 Datasheet - Page 30

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

STA310
ter). In this case, the latency is specified in the IEC958_LATENCY register.
Note that there are minimum and maximum values to respect
Table 7.
If those limits are not respected, an error interrupt occurs corresponding to error type: LATENCY_TOO_BIG,
which automatically makes the chip switch to auto_latency mode.
For software versions prior to 6, the latency is not implemented.
6.3 PCM null data
When configured in muted mode (in the IEC958_CMD register), the outputs are PCM null data. This can be
used to synchronize the external IEC receiver.
7
7.1 Interrupt register
The decoder can signal to the external controller that an interrupt has occurred during the execution.
The register INTE enables to select which interrupts will be generated and output on the IRQ output pin.
When an interrupt occurs, the signal IRQ is activated low and the controller can check which interrupt was de-
tected by reading the register INT.
According to the type of interrupt detected, other information can be obtained by reading associated registers
(such as stream header, type of error detected, PTS value).
7.2 IRQ Signal
This signal, IRQ, is a three-state line. This signal indicates (by going low) when an interrupt occurs. It returns to
high level once the corresponding bit in the interrupt register has been cleared.
7.3 Error concealment
Errors are signaled as interrupts by the audio core. The error list is provided in. Most of the errors are automat-
ically handled by the core, some require that software be changed.
AC-3 decoding errors:
Those errors are signaled in the ERROR register but handled directly by the core. Nothing can be done by the
software. They signal that something wrong happened during the decoding. The core soft mutes the frame and
continues to decode.
MPEG decoding errors:
Those errors are also signaled in the ERROR register but handled directly by the core. Nothing can be done by
the software. They signal that something wrong happened during the decoding. The core soft mutes the frame
and continues to decode. Only one error in this category indicates a programming error: if triggering the
30/90
256
samples / Fs
INTERRUPTS
Min. Latency
AC-3
1536
samples / Fs
Max. Latency
96
samples / Fs
Min. Latency
MPEG
1152
samples / Fs
Max. Latency