STA310 STMicroelectronics, STA310 Datasheet - Page 53

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

Type: R/W
Software Reset: 0
Hardware Reset: 0
Description:
This register enables to exit from idle mode. After a
soft or hard reset the decoder is in idle mode. It stays
in this mode until the RUN is set.
In run mode the decoder takes into account the state
of all the configuration registers and begins to de-
code.
The RUN register can only be reset by the SOFTRE-
SET command.
SKIP_MUTE_CMD
Skip or mute commands
Address: 0x73
Type: R/W
Software Reset: 0
Hardware Reset: 0
Description:
This register cannot be used in MP3 decoding
mode.The register is taken into account at a begin-
ning of decoding a frame.
SKIP_MUTE_VALUE
reserved
SMUT,
MUTE
SKP
BLK
PAU
Reserved Set to ’0’.
Value
7
6
If one or both of these bits is ’1’ then the
decoder continues the normal decoding
process, but the output samples are soft-
muted to zero. When both these bits are ’0’
muting is disabled and the decoder plays
the incoming frame.
Skip frame. The decoder skips the number
of frames programmed in register
Pause block. The decoder introduces a
delay equal to the number of blocks
programmed in register
The decoder is stopped whilst this bit is ’1’.
MUTE reserved PAU BLK SKP SMUT
5
4
Description
3
2
1
0
Skip frames or mutes blocks of frame
Address + 0x74
Type: R/W
Software Reset: 0
Hardware Reset:0
Description:
The value in this register gives either the number of
frames to skip or the number of blocks during which
the decoder will be stopped. This is used in conjunc-
tion with register .
9.10 Interrupt register
INTE
Interrupt enable
Address: 0x08 - 0x07
Type: R/W
Software Reset: 0
Hardware Reset: 0
Description:
This register is used to enable each interrupt inde-
pendently. Setting a bit in the register enables the
corresponding interrupt.
INT
Interrupt
Address: 0x0A - 0x09
Type: RO
Software Reset: 0
Hardware Reset:0
@0x0A
@0x08
@0x07
@0x09
7
6
7
7
5
6
6
4
5
5
INTE[15:8]
INTE[15:8]
INTE[7:0]
INTE[7:0]
4
4
3
3
3
2
2
2
1
STA310
1
1
53/90
0
0
0