STA310 STMicroelectronics, STA310 Datasheet - Page 49

IC AUDIO DECODER 6+2CH 80-TQFP

STA310

Manufacturer Part Number
STA310
Description
IC AUDIO DECODER 6+2CH 80-TQFP
Manufacturer
STMicroelectronics
Type
Audio Decoderr
Datasheet

Specifications of STA310

Applications
HDTV, Players, Receivers, Set-Top Boxes
Voltage - Supply, Analog
2.5V
Voltage - Supply, Digital
2.5V
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Audio Codec Type
MP3 Decoder
No. Of Dacs
3
No. Of Input Channels
2
No. Of Output Channels
6
Adc / Dac Resolution
32bit
Sampling Rate
192kHz
Interface Type
I2C, Serial, Parallel
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8856
STA310

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA310
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STA310
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA3100J
Manufacturer:
ST
0
Hardware: Reset:UND
Description:
The table below shows the relationship between the value of the IEC divider and the value of the PCM divider.
SPDIF_STATUS
SPDIF status bit
Address: 0x61
Type: R/W
Software Reset: NC
Hardware: Reset UND
Description:
DIV[4:0]
RND
SM
LAT
5
3
2
1
Bitfield
7
PCM Divider Value
This field is the DAC_PCMCLK divider. It must be set according to the formula:
in 16 bit mode: IECDIV=(1+PCMDIV)/2-1; in 32 bit mode: IECDIV=PCMDIV
This bit is used to have a "16-bit rounding" on the SPDIF (when in PCM mode):
0: no rounding,
1: rounding.
This bit has no effect on the precision of analogue data
SYNC MUTE Mode, must be set to zero.
Configures the latency mode between the SPDIF output (in mode compressed) and the Audio output.
0: Auto-Latency: The latency is the transmission time for 2/3 of the payload, plus the time to decode
an audio block.
For MPEG Auto-Latency, the latency is the following time depending of the sampling frequency in the
incoming bitstream: MPEG 48KHz: 20.90ms, MPEG 44.1KHz: 22.95ms, MPEG 32KHz: 32.53ms.
1: User-programmable latency - the
6
5
DAC_PCMCLK = 384Fs, DAC is 16-bit mode
DAC_PCMLK = 256 Fs, DAC is 16-bit mode
DAC_PCMLK = 384 Fs, DAC is 32-bit mode
DAC_PCMLK = 256 Fs, DAC is 32-bit mode
SFR
Mode Description
4
SPDIF_LATENCY register is used.
Description
3
PRE
2
2
1
2
1
IEC Divider Value
COP
1
STA310
COM
0
49/90

Related parts for STA310