STA310 STMicroelectronics, STA310 Datasheet - Page 44

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

STA310
– External crystal provide a clock running at
AU_PLL_FRACL_176
Frac Low Coefficient
Address: 0xBB
Type: R/W
Software Reset: 0x3
Hardware Reset: UND
Description:
This register must contain a FRACL value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
– External crystal provide a clock running at
AU_PLL_FRACH_176
Frac High Coefficient
Address: 0xBC
Type: R/W
Software Reset: 0x9
Hardware Reset: UND
Description:
This register must contain a FRACH value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
– External crystal provide a clock running at
AU_PLL_XDIV_176
44/90
384 x SF (where SF is the sampling frequency)
27MHz
384 x SF (where SF is the sampling frequency)
27MHz
384 x SF (where SF is the sampling frequency)
27MHz
7
7
6
6
5
5
4
4
FRACH
FRACL
3
3
2
2
1
1
0
0
X Divider Coefficient
Address: 0xBD
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
– External crystal provide a clock running at
AU_PLL_MDIV_176
M Divider Coefficient
Address: 0xBE
Type: R/W
Software Reset: 0x09
Hardware Reset: UND
Description:
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
– External crystal provide a clock running at
AU_PLL_NDIV_176
N Divider Coefficient
384 x SF (where SF is the sampling frequency)
27MHz
384 x SF (where SF is the sampling frequency)
27MHz
7
7
7
6
6
6
5
5
5
4
4
4
MDIV
NDIV
XDIV
3
3
3
2
2
2
1
1
1
0
0
0