HMP8117CNZ Intersil, HMP8117CNZ Datasheet - Page 35

• Manufacturer Part Number: HMP8117CNZ
• Description: IC VIDEO DECODER NTSC/PAL 80PQFP
• Manufacturer: Intersil
• Type: Video Decoderr

Specifications of HMP8117CNZ

• Applications: Video
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15-10
15-9
NO.
NO.
NO.
NO.
NO.
NO.
BIT
BIT
BIT
BIT
BIT
BIT
7-6
5-0
7-0
9-8
7-0
7-0
8
Reserved
Even Field
WSS CRC Data
Assert BLANK
Output Signal
Reserved
Assert BLANK
Output Signal
Negate BLANK
Output Signal
Assert BLANK
Output Signal
Reserved
Assert BLANK
Output Signal
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
35
If even field WSS is enabled and present during NTSC operation, this register is loaded with the
six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written
to this register is ignored.
This 8-bit register is cascaded with Start H_BLANK High Register to form a 10-bit start horizontal
blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK
each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two
pixel resolution. The leading edge of HSYNC is count 000
This 2-bit register is cascaded with Start H_BLANK Low Register to form a 10-bit start horizontal
blank register. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each
scan line. The leading edge of HSYNC is count 000
This 8-bit register specifies the horizontal count (in 1x clock cycles) to negate BLANK each scan
line. For proper operation, bit 0 must always be set to “0”; therefore, the end of horizontal
blanking may only set with two pixel resolution. If bit 0 is set to “1”, the chroma/luma output data
may be swapped. The leading edge of HSYNC is count 000
This 8-bit register is cascaded with Start V_BLANK High Register to form a 9-bit start vertical
blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical
blank register.
TABLE 51. WSS_CRC_EVEN DATA REGISTER
TABLE 53. START H_BLANK MSB REGISTER
TABLE 56. START V_BLANK MSB REGISTER
TABLE 52. START H_BLANK LSB REGISTER
TABLE 55. START V_BLANK LSB REGISTER
TABLE 54. END H_BLANK REGISTER
SUB ADDRESS = 29
SUB ADDRESS = 30
SUB ADDRESS = 31
SUB ADDRESS = 32
SUB ADDRESS = 33
SUB ADDRESS = 34
HMP8117
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
.
H
.
H
.
0000000
000000
000000
April 19, 2007
RESET
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
STATE
4A
7A
00
02
11
1
FN4643.3
B
B
H
B
H
H
B
B
B