AD9847AKST Analog Devices Inc, AD9847AKST Datasheet - Page 25

• Manufacturer Part Number: AD9847AKST
• Description: IC CCD SIGNAL PROC 10BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9847AKST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 40MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7/3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

REV. A
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets in
the signal chain and to track low frequency variations in the CCD’s
black level. During the optical black (shielded) pixel interval on
each line, the ADC output is compared with a fixed black level
reference, selected by the user in the clamp level register. The
value can be programmed between 0 LSB and 63.75 LSB with
8-bit resolution. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD9847 optical black
clamping may be disabled using Bit D2 in the OPRMODE
register. When the loop is disabled, the clamp level register may
still be used to provide programmable offset adjustment.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse-
widths may be used, but clamp noise may increase, and the
ability to track low frequency variations in the black level will be
reduced. See the section on Horizontal Clamping and Blanking
and also the Applications Information section for timing examples.
A/D Converter
The AD9847 uses a high performance 10-bit ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.4 LSB. The ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range. See TPC 1 and TPC 2 for
typical linearity and noise performance plots for the AD9847.
SUPPLY
DRIVER
3V
OUTPUTS
DATA
0.1 F
10
Figure 21. Recommended Circuit Configuration for External Mode
H DRIVER
SUPPLY
RG DRIVER
SUPPLY
(MSB) D9
(LSB) D0
DVDD3
DVSS3
DIGITAL
SUPPLY
D1
D2
D3
D4
D5
D6
D7
D8
3V
10
11
12
1
2
3
4
5
6
8
9
7
0.1 F
48 47 46 45 44
13 14 15 16
PIN 1
IDENTIFIER
0.1 F
(Not to Scale)
17 18 19 20 21 22 23 24
AD9847
TOP VIEW
43 42 41 40
0.1 F
–25–
39 38 37
APPLICATIONS INFORMATION
External Circuit Configuration
The AD9847 recommended circuit configuration for external
mode is shown in Figure 21. All signals should be carefully
routed on the PCB to maintain low noise performance. The CCD
output signal should be connected to Pin 29 through a 0.1 µF
capacitor. The CCD timing signals H1–H4 and RG should be
routed directly to the CCD with minimum trace lengths, as shown
in Figures 22a and 22b. The digital outputs and clock inputs are
located on Pins 1–12 and Pins 36–44 and should be connected
to the digital ASIC, away from the analog and CCD clock signals.
The CLI signal from the ASIC may be routed under the package
to Pin 23. This will help separate the CLI signal from the H1–H4
and RG signal routing.
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9847. This ground plane should be as continuous as
possible, particularly around Pins 25 – 35. This will ensure that
all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All decoupling capacitors should be located
as close as possible to the package pins. Placing series resistors
close to the digital output pins (Pins 1–12) may help reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise.
Power supply decoupling is very important in achieving low noise
performance. Figure 21 shows the local high frequency decoupling
capacitors, but additional capacitance is recommended for lower
frequencies. Additional capacitors and ferrite beads can further
reduce noise.
0.1 F
36
35
34
33
32
31
30
29
28
27
26
25
SL
REFT
REFB
CMLEVEL
AVSS3
AVDD3
BYP3
CCDIN
BYP2
BYP1
AVDD2
AVSS2
5
3V
ANALOG
SUPPLY
HIGH-SPEED
CLOCKS
0.1 F 0.1 F 0.1 F
CLOCK
INPUT
0.1 F
1 F
1 F
6
3
INTERFACE
CLOCK
INPUTS
SERIAL
0.1 F
0.1 F
0.1 F
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
CCD
SIGNAL
AD9847