ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 53

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
[1]
Table 68:
Address: Value read from func0 or func1 of address 10h + 34h
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcFmInterval - Host Controller Frame Interval register bit allocation
11.1.14 HcFmInterval register
R/W
R/W
R/W
R/W
R/W
FIT
15
31
23
15
0
7
0
0
0
0
reserved
Table 67:
Address: Value read from func0 or func1 of address 10h + 30h
This register contains a 14-bit value that indicates the bit time interval in a frame, that is,
between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum
packet size that the Host Controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new
value over the present at each SOF. This provides the possibility for the Host Controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in
Bit
31 to 4
3 to 0
[1]
R/W
R/W
R/W
R/W
R/W
14
30
22
14
0
6
0
0
0
0
HcDoneHead - Host Controller Done Head register bit description
DH[3:0]
Symbol
DH[27:0]
reserved
R/W
R/W
R/W
R/W
R/W
13
29
21
13
0
5
0
0
0
1
Rev. 01 — 14 July 2005
Description
Done Head: When a TD is completed, the Host Controller writes the
content of HcDoneHead to the NextTD field of the TD. The Host
Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller
writes the content of this register to HCCA.
-
R/W
R/W
R/W
R/W
R/W
12
28
20
12
0
4
0
0
0
0
FSMPS[7:0]
DH[11:4]
FSMPS[14:8]
R/W
R/W
R/W
R/W
R/W
11
27
19
11
0
3
0
0
0
1
FI[13:8]
Table
68.
R/W
R/W
R/W
R/W
R/W
10
26
18
10
0
2
0
0
0
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
reserved
[1]
R/W
R/W
R/W
R/W
R/W
25
17
9
0
1
0
0
0
9
1
ISP1563
R/W
R/W
R/W
R/W
R/W
53 of 107
24
16
8
0
0
0
0
0
8
0