ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 56

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
Table 74:
Address: Value read from func0 or func1 of address 10h + 40h
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcPeriodicStart - Host Controller Periodic Start register bit allocation
11.1.17 HcPeriodicStart register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
Table 73:
Address: Value read from func0 or func1 of address 10h + 3Ch
This register has a 14-bit programmable value that determines when is the earliest time
for the Host Controller to start processing the periodic list. For bit allocation, see
Table 75:
Address: Value read from func0 or func1 of address 10h + 40h
Bit
31 to 14
13 to 0
Bit
31 to 14
13 to 0
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
reserved
P_S[13:0]
HcFmNumber - Host Controller Frame Number register bit description
HcPeriodicStart - Host Controller Periodic Start register bit description
Symbol
reserved
FN[13:0]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
-
Periodic_Start: After a hardware reset, this field is cleared. It is then set
by the HCD during the Host Controller initialization. The value is roughly
calculated as 10 % of HcFmInterval. A typical value is 3E67h. When
HcFmRemaining reaches the value specified, processing of the periodic
lists have priority over control or bulk processing. The Host Controller,
therefore, starts processing the interrupt list after completing the current
control or bulk transaction that is in progress.
Rev. 01 — 14 July 2005
Description
-
Frame Number: Incremented when HcFmRemaining is reloaded. It
must be rolled over to 0h after FFFFh. Automatically incremented
when entering the USBOPERATIONAL state. The content is written to
HCCA after the Host Controller has incremented Frame Number at
each frame boundary and sent an SOF but before the Host Controller
reads the first ED in that frame. After writing to HCCA, the Host
Controller sets SF (bit 2 of HcInterruptStatus).
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
P_S[7:0]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
P_S[13:8]
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
ISP1563
Table
R/W
R/W
R/W
R/W
56 of 107
24
16
0
0
8
0
0
0
74.