STM3220G-SK/IAR STMicroelectronics, STM3220G-SK/IAR Datasheet - Page 31

• Manufacturer Part Number: STM3220G-SK/IAR
• Description: DEV KIT STM32F207ZG KICKSTART
• Manufacturer: STMicroelectronics
• Series: IAR Kickstartr
• Type: MCUr

Specifications of STM3220G-SK/IAR

• Contents: Hardware, Software and Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32F207
• Other names: 497-11404

STM32F205xx, STM32F207xx
2.2.32
2.2.33
2.2.34
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared
with any other peripheral.
Universal serial bus on-the-go full-speed (OTG_FS)
The STM32F205xx and STM32F207xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable
endpoint setting and supports suspend/resume. The USB OTG full-speed controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE
oscillator. The major features are:
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Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F205xx and STM32F207xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and
high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and
features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using
the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Internal FS OTG PHY support
External FS OTG PHY support through an I
Doc ID 15818 Rev 6
2
C connection
Description
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