STM3220G-SK/IAR STMicroelectronics, STM3220G-SK/IAR Datasheet - Page 95

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STM3220G-SK/IAR

Manufacturer Part Number
STM3220G-SK/IAR
Description
DEV KIT STM32F207ZG KICKSTART
Manufacturer
STMicroelectronics
Series
IAR Kickstartr
Type
MCUr
Datasheets

Specifications of STM3220G-SK/IAR

Contents
Hardware, Software and Documentation
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
STM32F207
Other names
497-11404
STM32F205xx, STM32F207xx
5.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 44.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 37. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
V
V
V
T
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
NRST_OUT
Symbol
F(NRST)
hys(NRST)
to the series resistance must be minimum
Table
R
PU
44. Otherwise the reset is not taken into account by the device.
10.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Generated reset pulse duration
Table
41).
Parameter
Doc ID 15818 Rev 6
(~10% order)
(2)
.
Reset source
V
Conditions
DD
V
DD
Internal
IN
> 2.7 V
supply voltage conditions summarized
=
Table 44
V
SS
are derived from tests
IL(NRST)
–0.5
Min
300
30
20
2
-
-
Electrical characteristics
max level specified in
Typ
200
40
-
-
-
-
-
V
DD
Max
100
0.8
50
-
-
-
+0.5
95/163
Unit
mV
ns
ns
µs
V

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