STM3220G-SK/IAR STMicroelectronics, STM3220G-SK/IAR Datasheet - Page 83

• Manufacturer Part Number: STM3220G-SK/IAR
• Description: DEV KIT STM32F207ZG KICKSTART
• Manufacturer: STMicroelectronics
• Series: IAR Kickstartr
• Type: MCUr

Specifications of STM3220G-SK/IAR

• Contents: Hardware, Software and Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32F207
• Other names: 497-11404

STM32F205xx, STM32F207xx
Table 30.
1. TBD stands for “to be defined”.
2. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Guaranteed by design, not tested in production.
4. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
5. Value given with main PLL running.
6. Based on characterization, not tested in production.
Jitter
Jitter
I
I
DD(PLLI2S)
DDA(PLLI2S)
Symbol
(4)
(5)
(6)
(6)
PLLI2S (audio PLL) characteristics
Cycle-to-cycle jitter
Period Jitter
Clock output on MCO pin (for
Ethernet applications)
Clock output on MCO pin (for
OTG FS applications)
Master I2S clock jitter
WS I2S clock jitter
PLLI2S power consumption on
V
PLLI2S power consumption on
V
DD
DDA
Parameter
Doc ID 15818 Rev 6
System clock
120 MHz
50 MHz
25 MHz
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
Average frequency of
12,343 MHz
N=432, P=4, R=5
on 256 samples
Cycle to cycle at 48 KHz
on 1000 samples
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
(1)
(continued)
Conditions
peak
to
peak
peak
to
peak
RMS
RMS
RMS
peak
peak
to
0.30
0.55
TBD
0.15
0.45
Min
-
-
-
-
-
-
-
-
-
Electrical characteristics
±150
±200
TBD
TBD
±280
Typ
400
25
15
90
-
-
-
Max
TBD
0.40
0.75
0.40
0.85
-
-
-
-
-
-
-
-
-
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Unit
mA
mA
ps
ps
ps
ps