SDKZSPF LSI, SDKZSPF Datasheet - Page 159

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 8.6
13
13
13
Cond
DEFAULT
WAIT_ON_MSS_RETRY
MID32_FETCH_PC
STRAD_NIC_FETCH_PCP8
NO_VAL_INST_FETCH_PC
PCP8_IC_NO_PREFETCH
PCP8_NIC_PREFETCH
PCP8_NIC_CLUNV_NO_PREFECH
VDISC_WAIT
VDISC_IC_NO_PREFETCH
VDISC_NIC_PREFETCH
VDISC_NIC_CLUNV_NO_PREFETCH
(9) 0x0000000e movlw
(10) 0x00000010 movhw
Grouping Rule: 19.1 (2 instructions in G stage).
PFU State Machine
ZSIM Commands
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
bits. The last line displays cache line pointers associated with the
state machine.
pipe
Displays information from the pipeline unit, such as cycle-by-cycle
grouping rule information of instructions issued in the G stage.
The first number is the cycle count. The second number, in
parentheses, is the instruction sequence number. The third number,
in hexadecimal, is the instruction address. The last column shows
the unit in which the instruction is executed.
a4, 0x20
a0, 0x0
Description
Default condition.
Prefetch queue is full or memory subsystem asserts retry for
a request.
Current PC lands into the middle of a 32-bit instruction.
The second half of a 32-bit instruction that straddles a cache
line is not in cache.
Current PC is not in cache.
Current PC+8 is in cache, no need to prefetch.
Current PC+8 is not in cache, prefetch that address.
Current PC+8 is not in cache. Machine can not prefetch
because that line is unavailable.
Wait for a loop or register based discontinuity.
Target of an immediate discontinuity is in cache, no need to
prefetch.
Target of an immediate discontinuity is not in cache.
Target of an immediate discontinuity is not in cache, but it
maps to a line that is not available
AGU0
AGU1
8-17