SDKZSPF LSI, SDKZSPF Datasheet - Page 277

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

other windows will not. When in hardware break mode, single stepping
is allowed by selecting “Step 1 clock cycle”. After each single step
operation, the register contents only will be refreshed. To return to normal
software debugging, select “Exit HW Mode”. This sends the hw
return_to_sw_dbg command to the command line debugger.
Figure 12.19
ZSP G2 Hardware Breakpoint Window
ZSP G2 Hardware breakpoints are used to stop the clocks to the G2 core
at a designated execution point. In order to resume execution, the
debugger sends a DEU RESTART command to the DEU.
Instruction Address Breakpoints
The ZSP500 DEU provides four 24-bit instruction address breakpoints.
Each instruction address breakpoint comprises an address, enable, and
16-bit counter. The breakpoint activates when the counter is zero. The
counter (when non-zero) decrements each time the breakpoint address
is encountered until it reaches zero. The breakpoint counter register
Detailed Descriptions
12-17
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