SDKZSPF LSI, SDKZSPF Datasheet - Page 183

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

0x2002
0x2003
zsim{3}> _
zsim{3}> show pipe
------------------------------------------ F(0:0)
------------------------------------------ G(0:0)
------------------------------------------ R(0:0)
------------------------------------------ E(0:0)
------------------------------------------ W(0:0)
zsim{4}> show icache
I$[0]: ------ I ------ I ------ I ------ I ------
I$[1]: ------ I ------ I ------ I ------ I ------
I$[2]: ------ I ------ I ------ I ------ I ------
I$[3]: ------ I ------ I ------ I ------ I ------
I$[4]: ------ I ------ I ------ I ------ I ------
I$[5]: ------ I ------ I ------ I ------ I ------
I$[6]: ------ I ------ I ------ I ------ I ------
I$[7]: ------ I ------ I ------ I ------ I ------
zsim{5}> show dcache
R13 - D$[ 0]: ------ I ------ ------ ------ ------
R13 - D$[ 1]: ------ I ------ ------ ------ ------
R13 - D$[ 2]: ------ I ------ ------ ------ ------
R14 - D$[ 3]: ------ I ------ ------ ------ ------
R14 - D$[ 4]: ------ I ------ ------ ------ ------
R14 - D$[ 5]: ------ I ------ ------ ------ ------
R15 - D$[ 6]: ------ I ------ ------ ------ ------
R15 - D$[ 7]: ------ I ------ ------ ------ ------
R15 - D$[ 8]: ------ I ------ ------ ------ ------
UL - D$[ 9]: ------ I ------ ------ ------ ------
UL - D$[10]: ------ I ------ ------ ------ ------
UL - D$[11]: ------ I ------ ------ ------ ------
UL - D$[12]: ------ I ------ ------ ------ ------
UL - D$[13]: ------ I ------ ------ ------ ------
0xa6d0 mov
0x2460 movl
Before execution cycles begin, you can check to make sure that the
pipeline and caches are empty:
As shown above, the five stages of the execution pipeline are identified
with a single letter – F (Fetch/decode), G (Group), R (Read), E
(Execute), and W (Write Back) – followed by two integers representing
the number of instructions currently in that stage and the number of
instructions that advance to the next stage in the following cycle.
In the above example, the 8 lines of the instruction cache are shown to
be empty . The first column contains the address (four word boundary)
and the remaining four columns contain the corresponding instruction
opcodes. An ‘I’ to the left of a cell indicates an invalid instruction.
Example Session Using ZSIM
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
r13, 0x0
r4, 0x60
8-41