SDKZSPF LSI, SDKZSPF Datasheet - Page 79

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.9 Q15 Support
write_creg(creg,val) - Puts a value, which can be a variable or
an immediate, into a control register. The val argument can be made by
or-ing together the following masks for the following registers:
Macros have also been defined to manipulate specific bits of control
registers.
bitset_creg(creg,bitnum)
bitclear_creg(creg,bitnum)
bitinvert_creg(creg,bitnum)
The bitnumber and value arguments can be filled with macros which
have been defined to the appropriate value. The bitnumber and mask to
access a specific bit has been defined to “bit name”_[MASK|BIT]. For
example, to set the Q15 bit of %fmode, use the following macro:
bitset_creg(%fmode,Q15_BIT);
CC supports the Q15 data type. To use Q15 arithmetic, the q15 mode bit
in the %fmode register must be set, as follows:
The q15 mode bit affects Q15 multiplies and the N-Instrinsics N_mul,
N_mac, N_macn, N_mac2, and the vector intrinsics.
Q15 arithmetic can be disabled as follows:
Q15 Support
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
%fmode: MRE_MASK, SRE_MASK, Q15_MASK, SAT_MASK,
REZ_MASK
%amode: RCA_LD_MASK, RCA_ST_MASK, RCA_REV_MASK,
CB0_MASK, CB1_MASK CB2_MASK, CB3_MASK
%smode: DDR_MASK, DIR_MASK, SIS_MASK, LIS_MASK,
US_MASK, UVT_MASK, DSB_MASK, ICT_MASK, FIE_MASK,
DCT_MASK, LVL_MASK
%imask: PGIE_MASK, GIE_MASK
bitset_creg(%fmode,Q15_BIT);
bitclear_creg(%fmode,Q15_BIT);
3-25