LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 152

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attribute is only used when
the pin assignments are made in HDL source. Pins assignments can be made directly using the GUI in the Prefer-
ence Editor of the software. The appendices explain this in more detail.
Design Considerations and Usage
This section discusses some of design rules and considerations that need to be taken into account when designing
with the LatticeECP/ECP and LatticeXP sysIO buffer.
Banking Rules
Differential I/O Rules
Assigning V
Each bank has two dedicated V
V
PGROUP preference.
Preference Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example of VREF Groups
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)”
COMP “ah(4)” COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)”
COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
LOCATE VREF “ref2” SITE PR48B;
REF1
• If V
• If V
• When implementing DDR memory interfaces, the V
• Only the top and bottom banks (Banks 0, 1, 4, and 5) will support PCI clamps. The left and right side (Banks
• All the banks can support LVDS input buffers. Only the banks on the right and left side (Banks 2, 3, 6 and 7)
• All banks support emulated differential buffers using external resistor pack and complementary LVCMOS
• In LatticeXP devices, not all PIOs have LVDS capability. Only four out of every seven I/Os can provide LVDS
or V
ply as V
ply as V
interface pins and cannot be used to power any other referenced inputs.
2, 3, 6 and 7) do not support PCI Clamp, but will support True LVDS output.
will support True Differential output buffers. The banks on the top and bottom will support the LVDS input
buffers but will not support True LVDS outputs. The user can use emulated LVDS output buffers on these
banks.
drivers.
buffer capability. In LatticeECP/EC devices, there are no restrictions on the number of I/Os that can support
LVDS. In both cases LVDS can only be assigned to the TRUE pad. Refer to the device data sheets to see
the pin listing for all the LVDS pairs.
CCIO
CCIO
REF2.
CCAUX,
CC,
REF
or V
or V
This grouping is done by assigning a PGROUP VREF preference along with the LOCATE
thus minimizing leakage.
CCJ
CCJ
/ V
thus minimizing leakage.
REF
for any bank is set to 3.3V, it is recommended that it be connected to the same power sup-
for any bank is set to 1.2V, it is recommended that it be connected to the same power sup-
Groups for Referenced Inputs
REF
input pins, V
REF1
and V
8-12
REF1
REF2.
of the bank is used to provide reference to the
Buffers can be grouped to a particular V
LatticeECP/EC and LatticeXP
sysIO Usage Guide
REF
rail,