LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 8

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice Semiconductor Design Floorplanning
Lattice Semiconductor FPGA Successful Place and Route
HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 15-8
Technical Support Assistance........................................................................................................................ 15-17
Introduction ...................................................................................................................................................... 16-1
Supported Architectures................................................................................................................................... 16-1
Related Documentation.................................................................................................................................... 16-1
Floorplanning Definition ................................................................................................................................... 16-1
Complex FPGA Design Management .............................................................................................................. 16-1
Floorplanning Design Flow............................................................................................................................... 16-2
When to Floorplan............................................................................................................................................ 16-2
Floorplan to Improve Design Performance ...................................................................................................... 16-3
Floorplan to Preserve Module Performance .................................................................................................... 16-3
Floorplan for Design Reuse ............................................................................................................................. 16-3
How to Floorplan a Design............................................................................................................................... 16-4
Special Floorplanning Considerations.............................................................................................................. 16-7
Summary.......................................................................................................................................................... 16-7
Technical Support Assistance.......................................................................................................................... 16-8
Introduction ...................................................................................................................................................... 17-1
ispLEVER Place and Route Software (PAR) ................................................................................................... 17-1
General Strategy Guidelines ............................................................................................................................ 17-2
Analyzing Timing Reports ................................................................................................................................ 17-6
Hierarchical Coding................................................................................................................................. 15-1
Design Partitioning .................................................................................................................................. 15-2
State Encoding Methodologies for State Machines ................................................................................ 15-3
Coding Styles for FSM ............................................................................................................................ 15-5
Using Pipelines in the Designs................................................................................................................ 15-6
Comparing IF statement and CASE statement ....................................................................................... 15-7
Avoiding Non-intentional Latches............................................................................................................ 15-8
Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 15-8
Implementing Multiplexers .................................................................................................................... 15-10
Clock Dividers ....................................................................................................................................... 15-10
Register Control Signals ....................................................................................................................... 15-12
Use PIC Features.................................................................................................................................. 15-14
Implementation of Memories................................................................................................................. 15-16
Preventing Logic Replication and Limited Fanout................................................................................. 15-16
Use ispLEVER Project Navigator Results for Device Utilization and Performance .............................. 15-17
Design Performance Enhancement Strategies ....................................................................................... 16-4
Design Floorplanning Methodologies...................................................................................................... 16-4
When to use PGROUP vs. UGROUP ..................................................................................................... 16-4
Floorplanner GUI Usage ......................................................................................................................... 16-6
Embedded Block RAM Placement .......................................................................................................... 16-7
I/O Grouping............................................................................................................................................ 16-7
Large Module Grouping .......................................................................................................................... 16-7
Carry Chains and Bus Grouping ............................................................................................................. 16-7
SLICs in Groups...................................................................................................................................... 16-7
Placement ............................................................................................................................................... 17-1
Routing.................................................................................................................................................... 17-1
Timing Driven PAR Process.................................................................................................................... 17-2
Typical Design Preferences .................................................................................................................... 17-2
Proper Preferences ................................................................................................................................. 17-3
Translating Board Requirements into FPGA Preferences ...................................................................... 17-4
Example 1. Multicycle Between Two Different Clocks ............................................................................ 17-6
Example 2. CLOCK_TO_OUT with PLL Feedback................................................................................. 17-8
7
LatticeXP Family Handbook
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