LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 172

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Memory Modules
Single Port RAM (RAM_DQ) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Single Port RAM or RAM_DQ.
IPexpress allows users to generate the Verilog-HDL or VHDL along an EDIF netlist for the memory size as per the
design requirements.
IPexpress generates the memory module as shown in Figure 9-7.
Figure 9-7. Single Port Memory Module generated by IPexpress
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks or primitives
and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes
smaller than an EBR block, the module will be created in one EBR block. In cases where the specified memory is
larger than one EBR block, multiple EBR block can be cascaded, in depth or width (as required to create these
sizes).
The memory primitive for RAM_DQ for LatticeECP/EC and LatticeXP devices is shown in Figure 9-8.
Figure 9-8. Single Port RAM Primitive or RAM_DQ for LatticeECP/EC and LatticeXP Devices
In Single Port RAM mode the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered.
AD[x:0]
CS[2:0]
DI[y:0]
RST
CLK
ClockEn
WE
Address
CE
Reset
Clock
Data
WE
EBR-based Single Port
EBR
9-7
RAM_DQ
Memory
LatticeECP/EC and LatticeXP Devices
DO[y:0]
Q
Memory Usage Guide