LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 224

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10-3. EC20 Pinout (from LatticeECP/EC Family Data Sheet)
DDR Software Primitives
This section describes the software primitives that can be used to implement DDR interfaces and provides details
about how to instantiate them in the software. The primitives described include:
An HDL usage example for each of these primitives is listed in Appendices B and C.
DQSDLL
The DQSDLL will generate a 90-degree phase shift required for the DQS signal. This primitive will implement the
on-chip DQSDLL. Only one DQSDLL should be instantiated for all the DDR implementations on one half of the
device. The clock input to this DLL should be at the same frequency as the DDR interface. The DLL will generate
the delay based on this clock frequency and the update control input to this block. The DLL will update the dynamic
delay control to the DQS delay block when this update control (UDDCNTL) input is asserted. Figure 10-5 shows
the primitive symbol. The active low signal on UDDCNTL updates the DQS phase alignment and should be initi-
ated at the beginning of READ cycles.
Figure 10-5. DQSDLL Symbol
Table 10-4 provides a description of the ports.
Table 10-4. DQSDLL Ports
DQSDLL Configuration Attributes
By default this DLL will generate a 90-degree phase shift for the DQS strobe based on the frequency of the input
reference clock to the DLL. The user can control the sensitivity to jitter by using the LOCK_SENSITIVITY attribute.
This configuration bit can be programmed to be either “HIGH” or “LOW”.
Ball Function
CLK
RST
UDDCNTL
LOCK
DQSDEL
• DQSDLL
• DQSBUF
• INDDRXB The DDR input and DQS to system clock transfer registers
• ODDRXB
PL11B
PL12A
Port Name
The DQS delay calibration DLL
The DQS delay function and the clock polarity selection logic
The DDR output registers
I/O
O
O
I
I
I
Bank
7
7
System CLK should be at frequency of the DDR interface, from the FPGA core.
Resets the DQSDLL
Provides an update signal to the DLL that will update the dynamic delay. When held low
this signal will update the DQSDEL.
Indicates when the DLL is in phase
The digital delay generated by the DLL should be connected to the DQSBUF primitive.
CLK
RST
UDDCNTL
LVDS
C
T
DQSDLL
10-5
Dual Function
DQSDEL
LOCK
—
—
Definition
LatticeECP/EC and LatticeXP
484 fpBGA
G3
H6
DDR Usage Guide
672 fpBGA
K4
J5