LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 317

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
nous to the clock; select OFF to synchronously wake up when the internal Done bit is set and ignore any external
driving of the DONE pin. The default is DONE_EX = OFF. If DONE_EX is set to ON, DONE_OD will be set to ON.
If an external signal is driving the DONE pin it should be open drain as well (an external pull-up resistor may need
to be added). See Table 13-11 for more information on the relationship between DONE_OD and DONE_EX.
Table 13-11. Summary of DONE pin Preferences (Preferences)
DONE_EX
Wake Up Process
DONE_OD
OFF
External DONE ignored
User selected
ON
External DONE low delays
Set to Default (ON)
Master Clock Selection
When the user has determined that the LatticeXP will be a master configuration device (by properly setting the
CFG[1:0] pins), and therefore provide the source clocking for configuration, the CCLK pin becomes an output with
the frequency set by the value in MCCLK_FREQ. At the start of configuration the device operates at the default
Master Clock Frequency of 2.5 MHz. Some of the first bits in the configuration bitstream are MCCLK_FREQ, once
these are read the clock immediately starts operating at the user-defined frequency. The clock frequency is
changed using a glitchless switch.
Security
When CONFIG_SECURE is set to ON, NO read back operation will be supported through the sysCONFIG or
ispJTAG port of the general contents. The ispJTAG DeviceID area is readable and not considered securable.
Default is OFF.
Wake Up Sequence
The WAKE_UP sequence controls three internal signals and the DONE pin. The DONE pin will be driven after con-
figuration and prior to user mode. See the Wake Up Sequence section of this document for an example of the
phase controls and information on the wake up selections. The default setting for the WAKE_UP preference is
determined by the DONE_EX setting.
Wake Up with DONE_EX = Off (Default Setting)
The WAKE_UP preference for DONE_EX = OFF (default) supports the user selectable options 1 through 25, as
shown in Table 13-8. If the user does not select a wake-up sequence, the default, for DONE_EX = OFF, will be
wake-up sequence 21.
Wake Up with DONE_EX = On
The WAKE_UP preference for DONE_EX = ON supports the user selectable options 1 through 7, as shown in
Table 13-8. If the user does not select a wake-up sequence, the default will be wake-up sequence 4.
Start_Up Clock Selection
Once the FPGA is configured, it enters the start-up state, which is the transition between the configuration and
operational states. This sequence is synchronized to a clock source, which defaults to CCLK when sysCONFIG is
used, or TCK when JTAG is used.
If desired, a user-defined clock source can be used instead of CCLK/TCK. You need to specify this clock signal,
and instantiate the STRTUP library element in your design. The example shown below shows the proper syntax of
instantiating the STRTUP library element.
Verilog:
STRTUP u1 (.UCLK(<clock_name>)) /* synthesis syn_noprune=1 */;
13-18