LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 366

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 18-3. Timing Arcs for Address and Command Signals
Figure 18-4. Timing Diagram for Address and Command Signals
Set-up Calculation
Therefore:
Isolating the board delays, we get:
Max Delay of Clock to DDR = t
Max Delays of command signals Data to DDR = t
To meet set up time at DDR memory, Clock Delay - Data Delay > 0
t
t
t
t
DDR_CLK
BDCTRL
BDCTRL
BDCTRL
command_signals
command_signals
At DDR Interface
pll_mclk (clkx)
t
- t
- t
- t
t
CCTRL
CCTRL
(max) + t
Symbol
BDC
BDC
BDC
t
At FPGA
BDCTRL
ddr_ad,
ddr_ad,
ddr_clk
CLK
(max)
< t
< 2.47 + 3.75 - 0.3 - 0.75 - 4.834
< 0.336 ns
(min)
DDR_CLK
BDC
+ t
Is the clock-to-out time for ddr_ad and command signals. 
(Clock Path Delay - Feedback Path) + Data Path Delay
Is the clock-to-out time for ddr_ad and command signals. 
(Clock Path Delay - Feedback Path) + Data Path Delay
Is the board delay of ddr_ad and command signals from 
FPGA pins to DDR SDRAM pins.
(max) + t
CK
* 1/2 - t
t
DDR_CLK
DDR_CLK
CK
SKEW
+ t
* 1/2 - t
BDC
t
(max) + t
CCTRL
- t
DS
SKEW
- t
Description
t
BDCTRL
CCTRL
18-6
BDC
- t
CCTRL
t
DS
DS
+ t
t
(max) - t
SKEW
- t
CK
(max) + t
CCTRL
for the DDR SDRAM Controller IP Core
* 1/2 - t
BDCTRL
(max)
BDCTRL
SKEW
> 0
- t
t
SKEW
DS
Board Timing Guidelines
t
DH
4.834 ns
2.147 ns
ORCA4
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