LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 260

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
This attribute is designed to select the Delay Adjustment mode. If the attribute is set to “DYNAMIC” the delay con-
trol switches between Dynamic and Static depending upon the input logic of DDAMODE pin. If the attribute is set to
“STATIC”, Dynamic Delay inputs are ignored in this mode.
LatticeECP/EC and LatticeXP PLL Primitive Definitions
The PLL primitive name is EHXPLLB. Figure 11-3 shows the LatticeECP/EC and LatticeXP PLL primitive library
symbol. Some features and I/Os are optional as described in Table 11-1 and Table 11-2.
Figure 11-3. LatticeECP/EC and LatticeXP PLL Primitive Symbol
Table 11-1. LatticeECP/EC and LatticeXP PLL I/O Definitions
PLL Attributes Definitions
The EHXPLLB can be configured through attributes in the source code. The following section details these attri-
butes and their usage.
Table 11-2. LatticeECP/EC and LatticeXP PLL Attributes
CLKI
CLKFB
RST
CLKOP
CLKOS
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
1. When internal feedback or clocktree feedback is selected in the IPexpress™ GUI, software uses CLKOP as the source of CLKFB. CLKOS
2. ModelSim
CLKI Frequency
CLKOP Frequency
CLKOK Frequency
CLKOP Frequency
Tolerance
is not recommended as the source of CLKFB even in external feedback mode.
Accessible
2
User
Signal
1
®
simulation models take two to four clock cycles from RST release to LOCK high.
GUI Access
IPexpress
Y
Y
Y
Y
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
FREQUENCY_PIN_CLKI
FREQUENCY_PIN_CLKOP
FREQUENCY_PIN_CLKOK
PLL reference clock input. From internal logic or dedicated clock pin.
Feedback clock input. From internal node, CLKOP or dedicated pin.
“1” to reset PLL
PLL output clock to clock tree
PLL output clock to clock tree with optional phase shift/duty cycle
PLL output clock to clock tree through K-divider for lower frequency
“1” indicates PLL locked to CLKI
DDA Mode. “1”: Pin Control (dynamic), “0”: fuse control (static)
DDA Delay Zero. “1” delay=0, “0”: delay=[DDILAG+DDAIDEL].
DDA Lag/Lead. “1”: Lead, “0”: Lag.
DDA Delay
DDA Delay Zero Output
DDA Lag/Lead Output
DDA Delay Output
Attribute
Name
RST
CLKI
CLKFB
DDAMODE
DDAIZR
DDAILAG
DDAIDEL2
DDAIDEL1
DDAIDEL0
Preference
Language
Support
N
N
N
N
EHXPLLB
11-4
Preference
Description
Support
Editor
N
N
N
N
sysCLOCK PLL Design and Usage Guide
DDAODEL2
DDAODEL1
DDAODEL0
DDAOLAG
DDAOZR
CLKOP
CLKOS
CLKOK
LOCK
0.0, 0.1, 0.2, 0.5, 1.0, 2.0, 5.0, 10.0
LatticeECP/EC and LatticeXP
Note 5
Note 5
Note 5
Value
Default
Value
100
100
0.0
50
Optional
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Units
MHz
MHz
MHz
%