LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 10

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-4. General Purpose PLL (GPLL) Diagram
Table 2-4 provides a description of the signals in the GPLL blocks.
Table 2-4. GPLL Block Signal Descriptions
Clock Dividers
LA-LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These
are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,
÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed
clock based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the
GPLLs or from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the
clock distribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The
RELEASE signal releases outputs to the input clock. For further information on clock dividers, see TN1126,
LatticeXP2 sysCLOCK PLL Design and Usage
CLKI
CLKFB
RST
RSTK
DPHASE [3:0]
DDDUTY [3:0]
WRDEL
CLKOS
CLKOP
CLKOK
CLKOK2
LOCK
DPHASE
WRDEL
DDUTY
CLKFB
RSTK
Signal
CLKI
RST
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Clock input from external pin or routing
DPA Phase Adjust input
DPA Duty Cycle Select input
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
“1” to reset PLL counters, VCO, charge pumps and M-dividers
“1” to reset K-divider
DPA Fine Delay Adjust input
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (no phase shift)
PLL output to clock tree through secondary clock divider
PLL output to clock tree (CLKOP divided by 3)
“1” indicates PLL LOCK to CLKI
CLKFB
Divider
Divider
CLKI
Internal Feedback
PFD
Guide. Figure 2-5 shows the clock divider connections.
LOOP FILTER
2-7
VCO/
Description
CLKOP
Divider
LA-LatticeXP2 Family Data Sheet
Detect
Lock
Duty Cycle/
Duty Trim
Duty Trim
CLKOK
Phase/
Divider
3
Architecture
CLKOK2
CLKOS
CLKOP
CLKOK
LOCK