LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 21

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Architecture
Lattice Semiconductor
LA-LatticeXP2 Family Data Sheet
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
(EBR clock). The reset
MAX
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP™ Block
The LA-LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast
Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo
Encoder/Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar
building blocks such as multiply-adders and multiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
• xed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LA-LatticeXP2 family, on the other hand, has many DSP blocks that support different
data-widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can
optimize the DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-19 compares the
fully serial and the mixed parallel and serial implementations.
Figure 2-19. Comparison of General DSP and LA-LatticeXP2 Approaches
Operand
Operand
Operand
A
A
A
Operand
Operand
Operand
B
B
B
Operand
Operand
A
B
x
x
x
m/k
Multiplier 0
loops
Multiplier 1
x
M loops
Single
Multiplier k
Multiplier
Accumulator
+ +
(k adds)
Function implemented in
General purpose DSP
m/k
accumulate
Output
Function implemented
in LA-LatticeXP2
sysDSP Block Capabilities
The sysDSP block in the LA-LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LA-LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not
2-18