LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 78

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Pin Information Summary
Single Ended User I/O
Differential Pair User I/O
Configuration
Non Configuration
Vcc
Vccaux
VCCPLL
VCCIO
GND, GND0-GND7
NC
Single Ended/
Differential I/O per Bank
True LVDS Pairs 
Bonding Out per Bank
Pin Type
Normal
Highspeed
TAP
Muxed
Dedicated
Muxed
Dedicated
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
csBGA
18/9
16/8
14/7
16/8
132
4/2
4/2
8/4
6/3
86
35
15
—
8
5
9
1
5
1
6
4
2
2
1
2
1
1
2
1
2
0
0
3
1
0
0
1
3
TQFP
20/10
18/9
18/9
18/9
100
144
6/3
4/2
8/4
8/4
39
11
15
—
LA-XP2-5
5
9
1
5
1
4
4
2
2
1
2
1
1
2
1
2
0
0
4
1
0
0
2
4
PQFP
20/10
20/10
18/9
18/9
16/8
18/9
18/9
18/9
146
208
57
16
20
5
9
1
7
1
9
4
2
2
2
2
2
2
2
2
2
4
0
0
4
4
0
0
4
4
4-4
ftBGA
26/13
22/11
20/10
24/12
22/11
22/11
18/9
18/9
172
256
66
20
20
31
5
9
1
7
1
6
4
2
2
2
2
2
2
2
2
0
0
5
5
0
0
5
5
-
csBGA
18/9
16/8
14/7
16/8
132
4/2
4/2
8/4
6/3
86
35
15
—
8
5
9
1
7
1
6
4
2
2
1
2
1
1
2
1
2
0
0
3
1
0
0
1
3
LA-LatticeXP2 Family Data Sheet
TQFP
20/10
18/9
18/9
18/9
144
100
6/3
4/2
8/4
8/4
39
11
15
—
LA-XP2-8
5
9
1
7
1
4
4
2
2
1
2
1
1
2
1
2
0
0
4
1
0
0
2
4
PQFP
20/10
20/10
18/9
18/9
16/8
18/9
18/9
18/9
208
146
57
16
22
5
9
1
9
1
9
4
2
2
2
2
2
2
2
2
2
2
0
0
4
4
0
0
4
4
Pinout Information
ftBGA
28/14
22/11
26/13
24/12
26/13
24/12
27/13
24/12
256
201
77
23
20
5
9
1
9
1
6
4
2
2
2
2
2
2
2
2
2
0
0
6
6
0
0
6
5
-
PQFP
20/10
20/10
18/9
18/9
16/8
18/9
18/9
18/9
208
146
LA-XP2-17
57
16
11
22
—
5
9
1
1
9
4
4
2
2
2
2
2
2
2
2
0
0
4
4
0
0
4
4
ftBGA
28/14
22/11
26/13
24/12
26/13
24/12
27/13
24/12
256
201
77
23
11
20
5
9
1
1
6
4
2
2
2
2
2
2
2
2
2
0
0
6
6
0
0
6
5
-