LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 64

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
EBR Timing Diagrams
Figure 3-6. Read/Write Mode (Normal)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-7. Read/Write Mode with Input and Output Registers
CLKA
DOA (Regs)
WEA
DOA
CSA
ADA
DIA
CLKA
WEA
ADA
CSA
DIA
t
SU
A0
D0
t
t
H
SU
A0
D0
t
H
Invalid Data
Mem(n) data from previous read
A1
D1
A1
D1
3-20
output is only updated during a read cycle
A0
t
A0
CO_EBR
t
COO_EBR
DC and Switching Characteristics
LA-LatticeXP2 Family Data Sheet
D0
A1
A1
t
CO_EBR
D0
D1
A0
A0
t
CO_EBR
t
COO_EBR
D1
D0