LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 69

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysCLOCK PLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v. A 0.12
IN
OUT
OUT2
VCO
PFD
DT
CPA
PH
OPJIT
SK
OPW
LOCK
IPJIT
FBKDLY
HI
LO
R
RSTKW
RSTW
Parameter
/ t
4
F
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP,
CLKOS)
K-Divider Output Frequency
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Coarse Phase Adjust
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
Input Clock Rise/Fall Time
Reset Signal Pulse Width (RSTK)
Reset Signal Pulse Width (RST)
LOCK
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
N/M = integer
90% to 90%
10% to 10%
10% to 90%
CLKOK
CLKOK2
Default duty cycle selected
f
100 MHz < f
At 90% or 10%
25 to 435MHz
10 to 25MHz
OUT
f
OUT
3-25
> 400 MHz
< 100 MHz
Conditions
OUT
< 400 MHz
DC and Switching Characteristics
LA-LatticeXP2 Family Data Sheet
3
0.078
Min.
435
500
3.3
0.5
0.5
10
10
10
45
10
—
—
—
—
—
—
—
—
—
-5
-5
1
Typ.
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
217.5
0.025
Max.
±125
±240
±200
±50
435
435
145
870
435
100
55
50
10
—
—
—
—
—
5
5
1
Units
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
ps
µs
µs
ns
ns
ns
ps
ps
ns
ps
ns
ns
ns
%
%
%