ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 141

• Manufacturer Part Number: ATMEGA328P-20PU
• Manufacturer: Atmel

Specifications of ATMEGA328P-20PU

• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Compliant

17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
17.1
17.2
8025K–AVR–10/09
Features
Overview
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Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
The PRTIM2 bit in
enable Timer/Counter2 module.
Figure 17-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
”Pinout ATmega48P/88P/168P” on page
”Minimizing Power Consumption” on page 42
”Register Description” on page
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
Direction
Count
Clear
Control Logic
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
clk
=
155.
Tn
ATmega48P/88P/168P
0
Figure
2. CPU accessible I/O Registers,
17-1. For the actual placement of
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
Waveform
Waveform
( From Prescaler )
Detector
Edge
must be written to zero to
OCnA
OCnB
Tn
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