ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 210
ATMEGA328P-20PU
Manufacturer Part Number
ATMEGA328P-20PU
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA328P-20PU.pdf
(419 pages)
Specifications of ATMEGA328P-20PU
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Program Memory Type
Flash
Program Memory Size
32KB
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Lead Free Status / Rohs Status
Compliant
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20.8.5
8025K–AVR–10/09
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 196.
ATmega48P/88P/168P
210
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