ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 68
ATMEGA328P-20PU
Manufacturer Part Number
ATMEGA328P-20PU
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA328P-20PU.pdf
(419 pages)
Specifications of ATMEGA328P-20PU
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Program Memory Type
Flash
Program Memory Size
32KB
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Lead Free Status / Rohs Status
Compliant
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12.2
12.2.1
8025K–AVR–10/09
Register Description
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-1.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-2.
Bit
(0x69)
Read/Write
Initial Value
ISC11
ISC01
0
0
1
1
0
0
1
1
Interrupt 1 Sense Control
Interrupt 0 Sense Control
ISC10
ISC00
R
7
–
0
0
1
0
1
0
1
0
1
Table
Table
Description
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
12-1. The value on the INT1 pin is sampled before detecting
12-2. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
4
–
0
ISC11
R/W
3
0
ATmega48P/88P/168P
ISC10
R/W
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
EICRA
68
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