ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 87

• Manufacturer Part Number: ATMEGA328P-20PU
• Manufacturer: Atmel

Specifications of ATMEGA328P-20PU

• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Compliant

8025K–AVR–10/09
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt
source.
• TXD/PCINT17 – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled,
this pin is configured as an output regardless of the value of DDD1.
PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt
source.
• RXD/PCINT16 – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this
pin is configured as an input regardless of the value of DDD0. When the USART forces this pin
to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt
source.
Table 13-10
shown in
Table 13-10. Overriding Signals for Alternate Functions PD7..PD4
Signal
Name
PUOE
PUO
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
PD7/AIN1
/PCINT23
0
0
0
0
0
0
PCINT23 • PCIE2
1
PCINT23 INPUT
AIN1 INPUT
and
Table 13-11
77.
relate the alternate functions of Port D to the overriding signals
PD6/AIN0/
OC0A/PCINT22
0
0
0
0
OC0A ENABLE
OC0A
PCINT22 • PCIE2
1
PCINT22 INPUT
AIN0 INPUT
ATmega48P/88P/168P
PD5/T1/OC0B/
PCINT21
0
0
0
0
OC0B ENABLE
OC0B
PCINT21 • PCIE2
1
PCINT21 INPUT
T1 INPUT
–
PD4/XCK/
T0/PCINT20
0
0
0
0
UMSEL
XCK OUTPUT
PCINT20 • PCIE2
1
PCINT20 INPUT
XCK INPUT
T0 INPUT
–
87