ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 208

• Manufacturer Part Number: ATMEGA328P-20PU
• Manufacturer: Atmel

Specifications of ATMEGA328P-20PU

• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Compliant

20.8
20.8.1
20.8.2
20.8.3
8025K–AVR–10/09
Register Description
UDRn – USART MSPIM I/O Data Register
UCSRnA – USART MSPIM Control and Status Register n A
UCSRnB – USART MSPIM Control and Status Register n B
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
normal USART operation. See “UDRn – USART I/O Data Register n” on page 192.
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCn
R
7
0
RXCIEn
R/W
7
0
TXCn
R/W
6
0
TXCIEn
R/W
6
0
UDREn
R
5
0
UDRIE
R/W
5
0
R
4
0
-
RXENn
R/W
4
0
R
3
0
-
ATmega48P/88P/168P
TXENn
R/W
3
0
R
2
1
-
R
2
1
-
R
1
1
-
R
1
1
-
R
0
0
-
R
0
0
-
UCSRnB
UCSRnA
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