P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 43
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P80C592FFA
Manufacturer Part Number
P80C592FFA
Description
Manufacturer
NXP Semiconductors
Datasheet
1.P80C592FFA.pdf
(108 pages)
Specifications of P80C592FFA
Cpu Family
80C
Device Core
80C51
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
CAN/UART
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
40
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / Rohs Status
Compliant
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Philips Semiconductors
13.5.10 B
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
Table 47 Bus Timing Register 1 (address 7)
Table 48 Description of the BTR1 bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
SAM
SAM
TSEG2.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2).
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
7
US
T
IMING
TSEG2.2
Sampling. If the bit SAM is:
TSEG1 determines the number of clock cycles per bit period and the location of the sample point
TSEG2 determines the number of clock cycles per bit period and the location of the sample point:
t
t
TSEG2
TSEG1
HIGH (3 samples), then three samples are taken. This is recommended for slow/medium speed
buses (SAE class A and B) where filtering of spikes on the bus-line is beneficial
(see Section 13.5.19.6)
LOW (1 sample), the bus is sampled once.
This is recommended for high speed buses (SAE class C).
R
6
EGISTER
=
=
t
t
SCL
SCL
1(BTR1)
TSEG2.1
4TSEG2.2
8TSEG1.3
5
+
+
2TSEG2.1
TSEG2.0
4TSEG1.2
4
43
+
+
TSEG2.0
2TSEG1.1
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
FUNCTION
TSEG1.3
3
+
+
1
TSEG1.0
.
TSEG1.2
2
+
1
.
TSEG1.1
1
Product specification
P8xC592
TSEG1.0
0