P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 72

• Manufacturer Part Number: P80C592FFA
• Manufacturer: NXP Semiconductors

Specifications of P80C592FFA

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: CAN/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

ndbook, halfpage
Philips Semiconductors
17.1
If the RST pin is connected to V
as shown in Fig.26, an automatic reset can be obtained by
switching on V
decrease of the RST pin voltage depends on the capacitor
and the internal resistor R
above the lower threshold for at minimum the oscillator
start-up time plus 2 machine cycles.
18 INSTRUCTION SET
The P8xC592 uses the powerful instruction set of the
P80C51. It consists of 49 single-byte, 45 two-byte and
17 three-byte instructions. Using a 16 MHz quartz, 64 of
the instructions are executed in 0.75 s, 45 in 1.5 s and
the multiply, divide instructions in 3 s. A summary of the
instruction set is given in Tables 84, 85, 86, 87 and 88.
1996 Jun 27
8-bit microcontroller with on-chip CAN
Power-on Reset
V DD
DD
Fig.26 Power-on-reset.
(provided its rise time is 10 ms). The
2.2 F
RST
RST
. That voltage must remain
P8xC592
DD
R RST
via a 2.2 F capacitor,
MGA171
V DD
72
18.1
Most instructions have a ‘destination/source’ field that
specifies the data type, addressing modes and operands
involved. For all these instructions, except from MOVs, the
destination operand is also a source operand
(e.g. ADD A, R7).
Five types of addressing modes are used:
The first three addressing modes are usable for
destination operands.
Register Addressing,
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte).
Direct Addressing,
– lower 128 bytes of internal MAIN RAM
– Special Function Registers (SFRs)
– 128 bits in a subset of the internal MAIN RAM
– 128 bits in a subset of the Special Function Registers
Register-Indirect Addressing,
– internal RAM (@R0, @R1, @SP PUSH/POP )
– internal AUXILIARY RAM (@R0, @R1, @DPTR)
– external Data Memory (@DPTR).
Immediate Addressing,
– Program Memory (in-code 8 bit or 16 bit constant).
Base-Register-plus Index-Register-Indirect Addressing,
– Program Memory look-up table
(including the 4 R0 to R7 register banks)
(see Fig.5)
(see Figs 6 and 7).
(@DPTR+A, @PC+A).
Addressing Modes
Product specification
P8xC592