P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 46

• Manufacturer Part Number: P80C592FFA
• Manufacturer: NXP Semiconductors

Specifications of P80C592FFA

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: CAN/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
13.5.12 T
The Test Register is used for production testing only.
Table 53 Test Register (address 9)
13.5.13 T
The global layout of the Transmit Buffer is shown in Fig.15. This buffer serves to store a message from the CPU to be
transmitted by the CAN-controller. It is subdivided into Descriptor and Data Field. The Transmit Buffer can be written to
and read from by the CPU.
13.5.13.1 Descriptor
Table 54 Descriptor Byte 1 Register (DSCR1, address 10)
Table 55 Descriptor Byte 2 Register (DSCR2, address 11)
Table 56 Description of the ID.n bits in DSCR1 and DSCR2
1996 Jun 27
Reserved
DSCR1
DSCR2
8-bit microcontroller with on-chip CAN
ID.10
ID.2
BIT
7
7
7
7
6
5
4
3
2
1
0
7
6
5
EST
RANSMIT
R
Reserved
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
ID.2
ID.1
ID.0
EGISTER
SYMBOL
B
ID.9
ID.1
UFFER LAYOUT
6
6
6
(TR)
Map Internal
Register
Identifier. The Identifier consists of 11 bits (ID.10 to ID.0). ID.10 is the most significant
bit, which is transmitted first on the bus during the arbitration process. The Identifier acts
as the messages' name, used in a receiver for acceptance filtering, and also determines
the bus access priority during the arbitration process. The lower the binary value of the
Identifier the higher the priority. This is due to the larger number of leading dominant bits
during arbitration (see Section 13.6.7).
Identifier. See DSCR1.
ID.8
ID.0
5
5
5
Connect RX
Buffer 0
CPU
RTR
ID.7
4
4
4
46
Connect TX
Buffer CPU
DLC.3
ID.6
3
3
3
FUNCTION
Access
Internal Bus
DLC.2
ID.5
2
2
2
Normal
RAM
Connect
DLC.1
ID.4
1
1
1
Product specification
P8xC592
Float Output
Driver
DLC.0
ID.3
0
0
0