ELANSC410-66AC AMD (ADVANCED MICRO DEVICES), ELANSC410-66AC Datasheet - Page 113

• Manufacturer Part Number: ELANSC410-66AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC410-66AC

• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. The signal names used in Figure 48 and Figure 49 are the PC/AT Compatible and Bidirectional mode signal names.
2. During EPP mode and Bidirectional mode, PPDWE acts as the parallel port chip select and is asserted for both reads and
3. These timings are only valid for EPP mode.
4. BUSY is asserted to add wait states to the parallel port access.
5. DBUFOE and DBUFRDL may be required when using the VESA local bus interface or a x32 DRAM interface.
writes. For PC/AT Compatible mode, PPDWE will be asserted only for parallel port write cycles.
Symbol
t10
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
Parameter Description
PPDWE delay from IOW
PPOEN delay from IOW
STRB delay from IOW
SLCTIN, AFDT valid from IOW
SD setup to IOW
SD hold from IOW
BUSY asserted from IOW asserted
IOW deasserted from BUSY deasserted
IOW pulse width
SLCTIN, AFDT recovery
DBUFOE setup to IOW
DBUFOE hold from IOW
PPDWE delay from IOR
SLCTIN, AFDT valid from IOR
SD setup to IOR deasserted
SD hold from IOR
BUSY asserted from IOR asserted
IOR deasserted from BUSY deasserted
IOR pulse width
DBUFOE, DBUFRDL setup to IOR
DBUFOE, DBUFRDL hold from IOR
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 40. Parallel Port Cycles
1
Notes
2
3
4
4
5
5
2
3
4
4
5
5
External Bus
1000
Min
100
450
100
450
50
50
20
20
20
10
2
2
2
2
2
2
0
0
33-MHz
Max
300
300
20
20
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
113