ELANSC410-66AC AMD (ADVANCED MICRO DEVICES), ELANSC410-66AC Datasheet - Page 64

• Manufacturer Part Number: ELANSC410-66AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC410-66AC

• Lead Free Status / Rohs Status: Not Compliant

64
Signal
Memory Interface
CASH3–CASH0
CASL3–CASL0
D31–D0
MA12–MA0
MWE
R32BFOE
RAS3–RAS0
ROMCS2–ROMCS0
ROMRD
ROMWR
VL-Bus Interface
VL_ADS
VL_BE3–VL_BE0
VL_BLAST
Type
O
O
O
O
O
O
O
O
O
O
O
O
B
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 19. Signal Description Table (Continued)
Description
Column Address Strobe High indicates to the DRAM devices that a valid column address
is asserted on the MA lines.
These CAS signals are for the odd banks (Banks 1 and 3); CASH3–CASH2 are for the high
word; and CASH1–CASH0 is for the low word.
Column Address Strobe Low indicates to the DRAM devices that a valid column address
is asserted on the MA lines.
These CAS signals are for the even banks (Banks 0 and 2); CASL1–CASL0 are for the low
word; CASL3–CASL2 are for the high word.
Data Bus is used for DRAM and local bus cycles. This bus is also used when interfacing to
32-bit ROMs.
Memory Address: The DRAM row and column addresses are multiplexed onto this bus.
Row addresses are driven onto this bus and are valid upon the falling edge of RAS. Column
addresses are driven onto this bus and are valid upon the falling edge of CAS.
Write Enable indicates an active write cycle to the DRAM devices. This signal is also used
to three-state EDO DRAMs at the end of EDO read cycles.
ROM 32-Bit Buffer Output Enable provides the buffer enable signal for the external
transceivers on the low word of the ROM interface. This signal is automatically provided
when the ROMCS0 interface is configured as 32 bit (the configuration can be done using
either CFG1–CFG0 or CSC index 20h[1–0]). Once ROMCS0 is configured as 32 bit, all
accesses to 32-bit ROM devices on ROMCS2–ROMCS0 result in the assertion of the
R32BFOE signal.
Row Address Strobe indicates to the DRAM devices that a valid row address is asserted
on the MA lines.
ROM Chip Selects are active Low outputs that provide the chip select for the BIOS ROM
and/or the ROM/Flash memory array. After power-on reset, the ROMCS0 chip select will go
active for accesses into the 64-Kbyte segment that contains the boot vector, at address
3FF0000h to 3FFFFFFh. ROMCS0 can be driven active during a linear (direct) address
decode of certain addresses in the high memory (00A0000h–00FFFFFh) region. By default,
direct-mapped accesses to the 64-Kbyte region from 00FFFF0h to 00FFFFFh are enabled
to support Legacy PC/AT BIOS. This area is known as the aliased boot vector. It can also be
activated by accessing a Memory Management System (MMS) page that points to the ROM0
address space. ROMCS1 is activated only when accessing an MMS page that points to it. A
third, MMS-mappable ROMCS2 signal is available by reconfiguring one of the chip’s General
Purpose Input Output (GPIO) pins for this function and also requires the use of MMS to
access devices connected to it.
ROM Read indicates that the current cycle is a read of the currently selected ROM device.
When this signal is asserted, the selected ROM device can drive data onto the data bus.
ROM Write indicates that the current cycle is a write of the currently selected ROM device.
When this signal is asserted, the selected ROM device can latch data from the data bus.
Local Bus Address Strobe is asserted to indicate the start of a VL-bus cycle. It is always
strobed Low for one clock period. The address and status lines are valid on the rising edge
of VL_LCLK, which samples this signal Low.
Local Bus Byte Enables indicate which byte lanes of the 32-bit data bus are involved with
the current VL-bus transfer.
Local Bus Burst Last is asserted to indicate that the next VL_BRDY assertion will terminate
the current VL-bus transfer.