ELANSC410-66AC AMD (ADVANCED MICRO DEVICES), ELANSC410-66AC Datasheet - Page 79

• Manufacturer Part Number: ELANSC410-66AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC410-66AC

• Lead Free Status / Rohs Status: Not Compliant

32-kHz Crystal Oscillator
The 32-kHz oscillator circuit is shown in Figure 6; the
only external component required for operation is a
32.768-kHz crystal. The inverting amplifier (AMP) is in-
tegrated on-chip together with the feedback resistor
and the load capacitors. As shown in Figure 7, the on-
chip oscillator circuit can be bypassed by removing the
external crystal, grounding the 32KXTAL1 pin, and
driving the 32KXTAL2 pin with an external 32-kHz
clock. (The 32KXTAL2 pin should not exceed 2.0 V.)
When 32KXTAL1 is grounded, the amplifier no longer
affects the circuit.
32KXTAL1
Loop Filters
Each of the PLLs in the ÉlanSC400 and ÉlanSC410 mi-
crocontrollers requires an external loop filter. For a
cleaner circuit, the designer should consider the following:
Place the loop filter components as close as
possible to the loop filter signals (LF_INT, LF_LS,
LF_HS, and LF_VID (ÉlanSC400 microcontroller
only)), which are located in one corner of the
microcontroller.
Route the loop filter signals first and by hand.
Keep all clocks and noisy signals away from the
loop filter area (even on the inner layers).
Oscillator
32 kHz
Figure 7. 32-kHz Oscillator Circuit
Figure 6. 32-kHz Crystal Circuit
32.768-kHz Crystal
AMP
Pin #Y4
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
2 V
max
32KXTAL1
32KXTAL2
32KXTAL2
External
Internal
For an even cleaner circuit, the designer could option-
ally place an analog V
loop filter circuit.
The value of the loop filter parameters can also affect
the performance of the filter. For example, the values of
C1 and R affect lock time and jitter (increasing RC in-
creases lock time and decreases jitter). The value of
C2 can help clean up high-frequency noise. Note that
using too large of values for the components can cause
the PLL to become unstable. The loop filter component
value specifications are shown in Table 28 on page 84.
Intermediate and Low-Speed PLLs
Figure 8 on page 80 shows the block diagram for both
the Intermediate and Low-Speed PLLs. Each consists
of a phase detector, a charge pump, a voltage con-
trolled oscillator (VCO), an external loop filter, and a
feedback divider. This is a generic implementation of
the charge-pump PLL architecture; all four PLLs use
the same architecture. The Intermediate and Low-
Speed PLLs differ only in component values and fre-
quency of operation.
The phase detector compares the phase and fre-
quency of the two clock signals, reference frequency
(Fr) and feedback frequency (Ff). The Up signal is a
logic 1 if Fr leads Ff, while the Down signal is a logic 1
if Ff leads Fr. The Up and Down signals control the
charge pump. The charge pump either charges or dis-
charges the loop filter capacitors to change the VCO
input voltage level. Because the VCO output frequency
tracks the VCO input voltage, the VCO output fre-
quency is adjusted whenever Fr and Ff differ in phase
or frequency.
The feedback divide ratio determines the frequency
multiplication factor.
Frequency multiplication is 1/(Feedback Divider).
For the Intermediate PLL, the feedback divider is 1/45;
therefore, the frequency multiplication is 45. With an
input frequency of 32.768 kHz, the output frequency is
1.47456 MHz.
The input clock for the Low-Speed PLL, Fr, originates
at the Intermediate PLL output. Fr is multiplied by 25 to
generate the 36.864-MHz clock output.
CC
power plane directly under the
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