SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 100

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Table 93 Timing parameters (t
Note
1. Only relevant to stretch access cycles in Intel mode. t
2004 Aug 25
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
as
ah
alh
az
dhw
dhr
dsw
dsrh
dsrd
idl
rwi
rdy
min
dz
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
edge of RDN/WRN.
address set-up time
address hold time
delay between de-asserting of RDN/WRN
and ALE
address 3-state time before start of read
command
write data output hold time
read data input hold time
write data output set-up time
read data input set-up time (relative to
handshake edge)
read data input set-up time (dumb target,
no handshake)
idle time before new transfer starts with
AS_ALE (increment mode)
idle time between two data access strobes
in non-increment mode; this parameter
depends on FAST mode enable
RDY assertion time (Intel mode)
delay from negative edge of RDN/WRN to
de-assertion of RDY; TIMEOUT should be
adjusted to TIMEOUT = t
time until slave driven data lines have to
go to 3-state, after read cycle is finished
PARAMETER
PCI
: PCI clock cycle time, minimum 30 ns)
min
+ 1
write access
read access
fast mode
normal mode
note 1
min
100
CONDITIONS
can be negative, i.e. RDY can be set to LOW before falling
t
t
t
t
0
t
20
2t
3t
t
2t
1.5t
PCI
PCI
PCI
PCI
PCI
PCI
3
0.7t
PCI
PCI
PCI
MIN.
PCI
PCI
15
10
15
10
15
10
10
10
10
(TIMEOUT
2.0 t
PCI
MAX.
Product specification
SAA7146A
0.5)t
PCI
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT