SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 52

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.8.2.2
In this mode only the HPS data path is available since the BRS data path supports only 8-bit wide data streams. Colour
difference signal and luminance signal (straight binary) are available in parallel on a 16-bit wide data stream. In this mode
both D1 ports are inputs (see Fig.9). With this format the pixel rate is half the clock rate LLC. The start condition for
synchronising the clock divider and/or the correct U-V sequence is given by the CREF signal, which must be connected
to the same port as the colour difference signal.
7.8.3
D1 (SMPTE125M, CCIR 656) as well as YUV16 represent both the same 4 : 2 : 2 sample scheme. Both formats,
D1 and YUV16, are assumed to agree with the CCIR recommendation 601 coding:
Data path processing in HPS and BRS is not limited to this range and allows overshoots and uses ‘margins’ for
processing. The reference values can be manipulated by the BCS processing in the HPS data path.
7.8.4
There are two timing reference codes; one at the beginning of each video data block [Start of Active Video (SAV)] and
one at the end of each video data block [End of Active Video (EAV)] as shown in Fig.10.
Each timing reference code consists of a four byte sequence in the following format: FF 00 00 XY. (values are expressed
in hexadecimal notation: codes FF, 00 are reserved for use in timing reference codes). The first three bytes are a fixed
preamble. The fourth byte contains information defining field identification, the state of field blanking and the state of line
blanking. The assignment of bits within the timing reference code is given in Table 51.
2004 Aug 25
handbook, full pagewidth
Y = 16 = black, 0%
Y = 235 = white, 100% brightness
U,V = 128 = no colour, 0% saturation
U,V = 128 112 = full colour, 100% saturation.
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
D1_B (7 to 0)
D1_A (7 to 0)
PXQ_A
(CREF)
V
V
HS_x
LLC
IDEO DATA FORMATS ON
IDEO TIMING REFERENCE CODES
YUV 16-bit parallel (DMSD2) stream
Cb0
Y0
Fig.9 Timing of PXQ_x for 16-bit data input at the D1_x port.
DD1
Cr0
Y1
(SAV
AND
EAV)
Cb2
Y2
52
Cr2
Y3
Cb4
Y4
Product specification
SAA7146A
Cr4
Y5
MHB051