SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 41

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Table 39 Secondary status register
2004 Aug 25
110
114
OFFSET
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
(HEX)
FIDA
FIDB
PIN3
PIN2
PIN1
PIN0
ECS
EC3S
EC0S
PRQ
PMA
RPS_RE1
RPS_PE1
RPS_A1
NAME
NAME
8
7
6
5
4
3
2
1
0
31
30
29
28
27
BIT
BIT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TYPE
TYPE
Field ID Port A: via the FIDESA bits in the ‘Initial setting of the
Dual D1 Interface’ (see Table 66), selected edge(s) of this
signal will set the corresponding bit in the ISR when enabled.
Field ID Port B: via the FIDESB bits in the ‘Initial setting of the
Dual D1 Interface’ (see Table 66), selected edge(s) of this
signal will set the corresponding bit in the ISR when enabled.
GPIO Pin 3: this bit reflects the state of the general purpose
pin 3. Via the GPIO register, selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
GPIO Pin 2: this bit reflects the state of the general purpose
pin 2. Via the GPIO register, selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
GPIO Pin 1: this bit reflects the state of the general purpose
pin 1. Via the GPIO register selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
GPIO Pin 0: this bit reflects the state of the general purpose
pin 0. Via the GPIO register selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
Event Counter Status: this bit reflects the status of the four
(SSR) event counter status bits EC5S, EC4S, EC2S and
EC1S.
Event Counter 3 Status: this bit is set when event counter 3
exceeds its threshold.
Event Counter 0 Status: this bit is set when event counter 0
exceeds its threshold.
PCI Request Pending: this bit is set while the PCI has asserted its
REQ# signal and has not received a GNT# yet
PCI master access: this bit is active as long as the SAA7146A acts as a
master on the PCI-bus
RPS Task 1 Register access Error: this bit is set when the LDREG,
STREG or MASKWRITE command tries to access a non-existing
register. This bit is reset by writing a logic 1 to the RPS_E1 bit in the ISR
or when a new RPS Task 1 is started.
RPS Task 1 Page Error: this bit is set when the RPS Task 1 tries to
write to an address outside the 4-kbyte page. This bit is reset by writing
a logic 1 to the RPS_E1 bit in the ISR or when a new RPS Task 1 is
started.
RPS Task 1 Active: this bit is set whenever RPS Task 1 is executing
and not staying in a wait condition or uploading the working registers
41
DESCRIPTION
DESCRIPTION
Product specification
SAA7146A
RESET