SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 57

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.8.8
This section describes how to choose the vertical offset and how to use the source line counter event for RPS
programming for capturing the expected line.
The internal Source Line Counter (SLC) is reset by the selected edge of the vertical sync signal which is provided at port
VS_x. The falling and rising edges of this signal are selected by the SYNC_X bits in the ‘Initial settings DD1 Port Register’
(offset = 50H). Consequently, the behaviour of the SLC depends on the connected vertical sync signal so that different
offsets must be selected to capture the expected line. The active video begins in the CCIR 656 line 23 of the video signal;
Table 54 lists the different offsets which must be selected to capture the expected line. The subsequent diagrams and
tables illustrate the relationship between the different vertical sync signals of the PAL and NTSC standards, the ODD and
EVEN field and the internal SLC.
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(1) LQ = qualified lines, i.e. lines containing at least one qualified pixel.
C
OMPARISON BETWEEN
CCIR 656
Fig.0 Reference signals for scaling window.
LINE AND SOURCE LINE COUNTER
HXO
BXO
ACTIVE VIDEO WINDOW
SCALING
WINDOW
line
NumBytes
57
HS_x
PXQ_x
frame
MHB055
field/
Product specification
SAA7146A