SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 43

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
2004 Aug 25
114
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
VF2
VF1
AF2_in
AF2_out
AF1_in
AF1_out
VGT
LNQG
EC5S
EC4S
EC2S
EC1S
NAME
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT
R
R
R
R
R
R
R
R
R
R
R
R
TYPE
Video FIFO 2 underflow/overflow: this bit is set when the video FIFO 2
has an overflow/underflow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
Video FIFO 1 overflow: this bit is set when the video FIFO 1 has an
overflow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
Audio input FIFO 2 underflow: this bit is set when the audio input
FIFO 2 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 2 overflow: this bit is set when the audio output
FIFO 2 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio input FIFO 1 underflow: this bit is set when the audio input
FIFO 1 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 1 overflow: this bit is set when the audio output
FIFO 1 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
reserved
Vertical Gate: this bit reflects the vertical gate at the HPS output
Line Qualifier Gate: this bit reflects the horizontal gate at the HPS
output
Event Counter 5 Status: this bit is set when event counter 5 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 4 Status: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 2 Status: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 1 Status: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
43
DESCRIPTION
Product specification
SAA7146A