AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 14

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

14
mains inactive. INV is sampled in the same clock period
that EADS is asserted. EADS has an internal weak pull-
up.
Note:
The triggering signal (AHOLD, HOLD, or BOFF) must
remain active for at least 1 clock after EADS to ensure
proper operation.
FERR
Floating-Point Error (Active Low; Output)
Driven active when a floating-point error occurs, FERR
is similar to the ERROR pin on a 387 math coprocessor.
FERR is included for compatibility with systems using
DOS-type floating-point error reporting. FERR is active
Low, and is not floated during bus hold, except during
three-state Test mode (see FLUSH).
FLUSH
Cache Flush (Active Low; Input)
In Write-back mode, FLUSH forces the microprocessor
to write-back all modified cache lines and invalidate its
internal cache. The microprocessor generates two flush
acknowledge special bus cycles to indicate completion
of the write-back and invalidation. In Write-through
mode, FLUSH invalidates the cache without issuing a
special bus cycle. FLUSH is an active Low input that
needs to be asserted only for one clock. FLUSH is asyn-
chronous, but setup and hold times t
met for recognition in any specific clock. Sampling
FLUSH Low in the clock before the falling edge of
RESET causes the microprocessor to enter three-state
Test mode.
HITM
Hit Modified Line (Active Low; Output)
In Write-back mode (WB/WT=1 at RESET), HITM indi-
cates that an external snoop cache tag comparison hit
a modified line. When a snoop hits a modified line in the
internal cache, the microprocessor asserts HITM two
clocks after EADS is asserted. The HITM signal stays
asserted (Low) until the last BRDY for the corresponding
write-back cycle. At all other times, HITM is deasserted
(High). During RESET, the HITM signal can be used to
detect whether the CPU is operating in Write-back
mode. In Write-back mode (WB/WT=1 at RESET), HITM
is deasserted (driven High) until the first snoop that hits
a modified line. In Write-through mode, HITM floats at
all times.
Trigger
AHOLD
HOLD
BOFF
Table 3. EADS Sample Time
Second clock after AHOLD asserted
First clock after HLDA asserted
Second clock after BOFF asserted
EADS First Sampled
Enhanced Am486DX Microprocessor Family
20
and t
21
P R E L I M I N A R Y
must be
HLDA
Hold Acknowledge (Active High; Output)
The HLDA signal is activated in response to a hold re-
quest presented on the HOLD pin. HLDA indicates that
the microprocessor has given the bus to another local
bus master. HLDA is driven active in the same clock in
which the microprocessor floats its bus. HLDA is driven
inactive when leaving bus hold. HLDA is active High and
remains driven during bus hold. HLDA is floated only
during three-state Test mode (see FLUSH).
HOLD
Bus Hold Request (Active High; Input)
HOLD gives control of the microprocessor bus to anoth-
er bus master. In response to HOLD going active, the
microprocessor floats most of its output and input/output
pins. HLDA is asserted after completing the current bus
cycle, burst cycle, or sequence of locked cycles. The
microprocessor remains in this state until HOLD is deas-
serted. HOLD is active High and does not have an in-
ternal pull-down resistor. HOLD must satisfy setup and
hold times t
IGNNE
Ignore Numeric Error (Active Low; Input)
When this pin is asserted, the Enhanced Am486DX mi-
croprocessors will ignore a numeric error and continue
executing non-control floating-point instructions. When
IGNNE is deasserted, the Enhanced Am486DX micro-
processors will freeze on a non-control floating-point
instruction if a previous floating-point instruction caused
an error. IGNNE has no effect when the NE bit in Control
Register 0 is set. IGNNE is active Low and is provided
with a small internal pullup resistor. IGNNE is asynchro-
nous but must meet setup and hold times t
ensure recognition in any specific clock.
INTR
Maskable Interrupt (Active High; Input)
When asserted, this signal indicates that an external
interrupt has been generated. If the internal interrupt
flag is set in EFLAGS, active interrupt processing is ini-
tiated. The microprocessor generates two locked inter-
rupt acknowledge bus cycles in response to the INTR
pin going active. INTR must remain active until the in-
terrupt acknowledges have been performed to ensure
that the interrupt is recognized. INTR is active High and
is not provided with an internal pull-down resistor. INTR
is asynchronous, but must meet setup and hold times
t
INV
Invalidate (Active High; Input)
The external system asserts INV to invalidate the cache-
line state when an external bus master proposes a write.
It is sampled together with A31–A4 during the clock in
20
and t
21
for recognition in any specific clock.
18
and t
19
for proper operation.
20
and t
21
to