AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 53

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

7.2
This section includes a detailed description of the bit
fields in the TR5.
Note: Bits listed in Table 19 as Reserved or Not Used
are not included in the descriptions.
Valid (bit 10): Read/Write, independent of the Ext bit
in TR5. This is the Valid bit for the accessed entry.
On a cache look-up, Valid is a copy of one of the bits
reported in bits 6–3. On a cache write in Write-
through mode, Valid becomes the new Valid bit for
the selected entry and set. In Write-back mode, writ-
ing to the Valid bit has no effect and is ignored; the
Set State bit locations in TR5 are used to set the
Valid bit for the selected entry and set.
LRU (bits 9–7): Read Only, independent of the Ext
bit in TR5. On a cache look-up, these are the three
LRU bits of the accessed set. On a cache write, these
bits are ignored; the LRU bits in the cache are up-
dated by the pseudo-LRU cache replacement algo-
rithm. Write operations to these locations have no
effect on the device.
Valid (bits 6–3): Read Only, independent of the Ext
bit in TR5. On a cache look-up, these are the four
Valid bits of the accessed set. In Write-back mode,
these valid bits are set if a cache set is in the exclu-
sive, modified, or shared state. Write operations to
these locations have no effect on the device.
Ext (bit 19): Read/Write, available only in Write-back
mode. Ext, or extension, determines which bit fields
are defined for TR4: the address TAG field, or the
STn and ST3–ST0 status bit fields. In Write-through
mode, the Ext bit is not accessible. The following
describes the two states of Ext:
— Ext = 0, bits 31–11 of TR4 contain the TAG ad-
— Ext = 1, bits 30–29 of TR4 contain STn, bits 27–
Set State (bits 18–17): Read/Write, available only in
Write-back mode. The Set State field is used to
change the MESI state of the set specified by the
Index and Entry bits. The state is set by writing one
of the following combinations to this field:
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
Index (bits 11–4): Read/Write, independent of Write-
through or Write-back mode. Index selects one of
the 256 cache lines.
Entry (bits 3–2): Read/Write, independent of Write-
through or Write-back mode. Entry selects between
dress
20 contain ST3–ST0
TR5 Definition
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
7.3
The following paragraphs provide examples of testing
the cache using TR4 and TR5.
7.3.1 Example 1: Reading The Cache (Write-Back
1. Disable caching by setting the CD bit in the CR0
2. In TR5, load 0 into the Ext field (bit 19), the required
3. Reading the Set State fields in TR4 during Write-
7.3.2 Example 2: Writing The Cache
1. Disable the cache by setting the CD bit in the CR0
2. In TR5, load 0 into the Ext field (bit 19), the required
3. Load the TR3 register with the data to write to the
4. Repeat steps 2 and 3 for the remaining three dou-
5. In TR4, load the required values into TAG field (bits
one of the four entries in the set addressed by the
Set Select during a cache read or write. During cache
fill buffer writes or cache read buffer reads, the value
in the Entry field selects one of the four doublewords
in a cache line.
Control (bits 1–0): Read/Write, independent of
Write-through or Write-back mode. The control bits
determine which operation to perform. The following
is a definition of the control operations:
— 00 = Write to cache fill buffer, or read from cache
— 01 = Perform cache write
— 10 = Perform cache read
— 11 = Flush the cache (mark all entries invalid)
register.
index into the Index field (bits 10–4), the required
entry value into the Entry field (bits 3–2), and 10 into
the Control field (bits 1–0). Loading the values into
TR5 triggers the cache read. The cache read loads
the TR4 register with the TAG for the read entry,
and the LRU and Valid bits for the entire set that
was read. The cache read loads 128 data bits into
the cache read buffer. The entire buffer can be read
by placing each of the four binary combinations in
the Entry field and setting the Control field in TR5
to 00 (binary). Read each doubleword from the
cache read buffer through TR3.
back mode is accomplished by setting the Ext field
in TR5 to 1 and rereading TR4.
register.
entry value into the Entry field (bits 3–2), and 00 into
the Control field (bits 1–0).
cache fill buffer. The cache fill buffer write is trig-
gered by loading TR3.
blewords in the cache fill buffer.
31–11) and the Valid field (bit 10). In Write-back
mode, the Valid bit is ignored since the Set State
field in TR5 is used in place of the TR4 Valid bit.
read buffer
Using TR4 and TR5 for Cache Testing
Mode Only)
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