AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 19

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

3.5.2.4
A modified line contains valid data for an external mem-
ory location. However, the data does not match the data
in the external location because the processor has mod-
ified the data since it was loaded from the external mem-
ory. A cache that contains a modified line is responsible
for ensuring that the data is properly maintained. This
means that in the case of an external access to that line
from another external bus master, the modified line is
first written back to the external memory before the other
external bus master can complete its access. Table 6
shows the MESI cache line states and the correspond-
ing availability of data.
3.6
The cache line replacement algorithm uses the standard
Am486 CPU pseudo LRU (Least-Recently Used) strat-
egy. When a line must be placed in the internal cache,
the microprocessor first checks to see if there is an in-
valid line available in the set. If no invalid line is available,
the LRU algorithm replaces the least-recently used
cache line in the four-way set with the new cache line.
If the cache line for replacement is modified, the modi-
fied cache line is placed into the copy-back buffer for
copying back to external memory, and the new cache
line is placed into the cache. This copy-back ensures
that the external memory is updated with the modified
data upon replacement.
3.7
In computer systems, memory regions require specific
caching and memory write methods. For example, some
memory regions are non-cacheable while others are
cacheable but are write-through. To allow maximum
memory configuration, the microprocessor supports
specific memory region requirements. All bus masters,
such as DMA controllers, must reflect all data transfers
on the microprocessor local bus so that the micropro-
cessor can respond appropriately.
3.7.1 Cacheability
The Enhanced Am486DX microprocessors cache data
based on the state of the CD and NW bits in CR0, in
conjunction with the KEN signal, at the time of a burst
read access from memory. If the WB/WT signal is Low
Line valid? Yes
External
memory
is...
A write to
this cache
line...
Situation Modified Exclusive
Cache Replacement Description
Memory Configuration
Table 6. MESI Cache Line Status
Modified
out-of-
date
does not
go to the
bus
Yes
valid
does not go
to the bus
Yes
valid
goes to
the bus
and
updates
Enhanced Am486DX Microprocessor Family
Shared
P R E L I M I N A R Y
No
status
unknown
goes
directly to
the bus
Invalid
during the first BRDY, KEN meets the standard setup
and hold requirements and the four 32-bit doublewords
are still placed in the cache. However, all cacheable
accesses in this mode are considered write-through.
When the WB/WT is High during the first BRDY, the
entire four 32-bit doubleword transfer is considered
write-back.
Note: The CD bit in CR0 enables (0) or disables (1) the
internal cache. The NW bit in CR0 enables (0) or dis-
ables (1) write-through and snooping cycles. RESET
sets CD and NW to 1. Unlike RESET, however, SRESET
does not invalidate the cache nor does it modify the
values of CD and NW in CR0.
3.7.2 Write-Through/Write-Back
If the CPU is operating in Write-back mode (i.e., the
WB WT pin was sampled High at RESET), the WB WT
pin indicates whether an individual write access is exe-
cuted as write-through or write-back. The Enhanced
Am486DX microprocessors do this on an access-by-
access basis. Once the cache line is in the cache, the
STATUS bit is tested each time the processor writes to
the cache line or a tag compare results in a hit during
Bus-watching mode. If the WB WT signal is Low during
the first BRDY of the cache line read access, the cache
line is considered a write-through access. Therefore, all
writes to this location in the cache are reflected on the
external bus, even if the cache line is write protected.
3.8
The description of cache functionality in Write-back
mode is divided into two sections: processor-initiated
cache functions and snooping actions.
3.8.1 Processor-Initiated Cache Functions and
The Enhanced Am486DX microprocessors contain two
new buffers for use with the MESI protocol support: the
copy-back buffer and the write-back buffer. The proces-
sor uses the copy-back buffer for cache line replacement
of modified lines. The write-back buffer is used when an
external bus master hits a modified line in the cache
during a snoop operation and the cache line is desig-
nated for write-back to main memory. Each buffer is four
doublewords in size. Figure 1 shows a diagram of the
state transitions induced by the local processor. When
a read miss occurs, the line selected for replacement
remains in the modified state until overwritten. A copy
of the modified line is sent to the copy-back buffer to be
written back after replacement. When reload has suc-
cessfully completed, the line is set either to the exclusive
or the shared state, depending on the state of PWT and
WB/WT signals.
Cache Functionality in Write-Back
Mode
State Transitions
19